1. Field of the Invention
The present invention relates to a self refresh oscillator and, more particularly, to a self refresh oscillator that can reduce power consumption by varying a self refresh period in accordance with a temperature change.
2. Discussion of Related Art
In general, data stored in a DRAM cell are erased by a leakage current, so that the data in the cell are sensed and amplified, and then rewritten in the cell. This operation refers to refresh.
There are three methods for performing the refresh operation, of which one is performed by inputting a row address from an external side, another (CBR refresh method) by inputting a control signal (i.e., CAS-Before-Ras (CBR) signal) for the refresh from the external side, and generating an address to be refreshed and then refreshing the address on an internal side, and the third, known as a hidden refresh method, by performing the CBR refresh in cooperation with normal operation.
Recently, while an external control signal is applied to the device in a constant state and maintained without any changes, a CBR state is periodically made within the device to perform the refresh operation. This method is called “self refresh”.
It is necessary to perform the refresh operation in the cell so as to prevent the data in the cell from being completely erased due to a leakage current generated in the cell. The leakage current is closely related to a temperature (i.e., whenever the temperature increases 10° C., the leakage current increases twice), and takes a major role in determining the refresh period.
When the memory device is fabricated, the circuit thereof must be safely operated even in an extreme situation. For example, the time capable of maintaining the data in the cell is reduced to half for the temperature increase of 10° C. and to 1/32 for the temperature increase of 50° C.
For example, if the refresh operation should be performed at a constant period with safety even at a high temperature in regardless of the temperature change, which means that many and unnecessary refresh operations should be performed at a room temperature or at a relatively low temperature.
In other words, for the safety of data in the case of having a constant refresh period in regardless of the temperature change, i.e., to have the memory device safely operate even at a high temperature, a lot of refresh operations are performed at a room temperature, which means that many and unnecessary powers be consumed even at a relatively low temperature.
FIG. 1 shows a circuit diagram of a self refresh oscillator in accordance with the prior art.
FIG. 1 shows the circuit for five self refresh oscillators in accordance with the prior art, and takes the form of a ring oscillator consisted of 5 staged inverters as a whole. Each inverter consists of a PMOS transistor connected to a VSS and an NMOS transistor connected to a VDD, and these transistors act as turn-on resistors for adjusting the period of the oscillator. The signal OSC_ON is one that controls turning on/off the oscillator, and the signals OSC and OSB are output signals.
In this circuit, when the signal OSC_ON becomes high, the ring type oscillator starts to operate and output a pulse signal of a waveform having a constant period.
The problem of the circuit is that the characteristic of the oscillator is constant in accordance with a temperature, so that the basic temperature characteristic of the DRAM cell is not significantly reflected.
FIG. 2 shows a graph of the refresh characteristic in accordance with the temperature of the DRAM cell, and it can be seen that the refresh characteristic is good when the temperature is low and not good when high. Thus, the amount of consumed current needs to be decreased by increasing the refresh time at a low temperature. However, the pulse period generated in the ring oscillator at a low temperature is the same as that at a high temperature, so that the current for the refresh operation is more consumed at the low temperature in the prior art.
Since the amount of current consumed for the refresh operation in the DRAM has a proportional relationship with how often the refresh operation is performed, the more the period for the refresh operation is lengthened, the less the amount of current consumed in the DRAM is decreased. However, if the refresh period is lengthened more than the effective value of the original refresh of the DRAM cell, data in the cell might be corrupted, so that it is important to set a proper refresh time and then determine a point where the data are not lost and the required current is small.
The prior art has focused on the prevention of data loss and maintained the setting value even at a low temperature that had been used at a high temperature when the effective value was not good, so that it does not utilize the characteristic that the cell has a good effective value for the refresh at a relatively low temperature. In other words, the circuit diagram of the prior art cannot implement the method that the refresh period be shortened at a high temperature and relatively lengthened at a low temperature.
FIG. 3 shows one of prior arts. The technology disclosed in FIG. 3 uses three staged oscillators, which use subthreshold leak currents of PMOS transistor and NMOS transistor (T1 and T4) inserted between each of the stages.
FIG. 4 shows a circuit diagram for another self refresh oscillator in accordance with the prior art, which models a DRAM cell and performs the refresh operation for the total cells when an electric potential of capacitors (VCP) modeling a leak current of the DRAM cell is lower than the reference voltage (VREF).
As mentioned above, this prior art also has a problem that the characteristic of the oscillator is constant in accordance with the temperature, so that the basic temperature characteristic of the DRAM cell is not significantly reflected.